Field of Art
The present disclosure relates to planarization processes.
Description of the Related Art
It is often necessary to planarize a substrate. For example, the process for creating a semiconductor device includes repeatedly adding and removing material to a substrate producing a layered substrate with an irregular height variation (topography). As more layers are added to the substrate the height variation increases. This height variation has a negative impact on the ability to add additional layers to the layered substrate. One method of addressing this issue is to planarize a feature laden substrate. Lithographic patterning methods benefit from patterning a planar surface. In ArFi laser based lithography, planarization improves depth of focus (DOF), critical dimension (CD), and critical dimension uniformity. In extreme ultra violet lithography (EUV), planarization improves feature placement and DOF. In nanoimprint lithography (NIL) planarization improves feature filling and CD control after pattern transfer.
In the semiconductor industry the most common way to planarize is chemical and mechanical polishing (CMP). There are some disadvantages to CMP as it addresses mainly hard materials like metals and dielectrics. It can be difficult to apply CMP to a soft material like a resist and requires careful and tight process controls which can be difficult and expensive to implement and maintain. Another limitation with CMP is that topography with large open features larger than a few microns show dishing, i.e. the planarization is not ideal. The dishing cannot be prevented unless the features are laterally smaller. An alternative planarization technique is required.
One alternative planarization technique is contact planarization CP as described in U.S. Pat. No. 5,736,424 by Judith Ann PRYBYLA et al. (hereinafter Prybyla). Prybyla discloses a first step of coating a non-planar surface with a planarizing liquid. A flat object is then brought into contact with the planarizing liquid. After which the planarizing liquid is cured. The flat object is then removed. According to Prybyla under certain circumstances this process can result in a planarization film with a thickness between 500 nanometer (nm) and 10 micrometer (μm) and variation in the range of 50-200 nm. Prybyla discloses that under certain ideal circumstances if the shrinkage of the planarizing liquid is less than 10%, then the degree of planarization can be up to 96%. As the industry has progressed, the planarization requirements have also progressed, such that the process described by Prybyla is no longer sufficient.
Another alternative planarization technique is adaptive inkjet-based planarization that includes dispensing a variable drop pattern of polymerizable material between a first surface and a template. The drop pattern varies depending on the topography of the first surface. The template is then brought into contact with the polymerizable material. After which the polymerizable material is solidified. The solidified polymerizable material and the underlying substrate are then etched so that it has a second surface which may be planar. The drop pattern may be adjusted to compensate for parasitic effects such as pattern density variations and volume shrinkage of the solidified polymerizable material. It has been suggested that, the volume shrinkage may be compensated for by deforming the template or adjusting the drop pattern. Although, how much deformation is needed has not been previously disclosed.
An exemplary nano-fabrication technique in use today is commonly referred to as nanoimprint lithography. Nanoimprint lithography is useful in a variety of applications including, for example, fabricating layers of integrated devices such as CMOS logic, microprocessors, NAND Flash memory, NOR Flash memory, DRAM memory, MRAM, 3D cross-point memory, Re-RAM, Fe-RAM, STT-RAM, and the like. Exemplary nanoimprint lithography processes are described in detail in numerous publications, such as U.S. Pat. Nos. 8,349,241, 8,066,930, and 6,936,194, all of which are hereby incorporated by reference herein.
Nanoimprint lithography technique disclosed in each of the aforementioned U.S. patents includes contacting an imprint template with a formable material. After the imprint template is brought into contact with the formable material, the formable material flows into indents within the imprint template so as to form a pattern. After the formable material has filled all of the indents within the imprint template, the formable material is cured. Other lithography techniques are optical lithography which may use ArFi, EUV optical sources.